1. Field of the Invention
The present invention relates to a test technology of semiconductor integrated circuits, and more particularly, relates to a test pattern generating apparatus, a method for automatically generating test patterns, and a computer program product for executing an application for a test pattern generating apparatus capable of automatically generating the test patterns.
2. Description of the Related Art
Recently, a large-scale integrated circuit (LSI) called a system on chip (SOC) has been widely developed. The LSI is frequently manufactured by use of a deep sub-micrometer (DSM) process using metal wires having a width less than or equal to 0.2 μm to 0.1 μm. With respect to the LSIs manufactured by the DSM process, it frequently occurs that elements and processes that have been not problems become serious problems at the sub-micrometer level. Similar problems occur to random logic circuits (logic circuit blocks arranged by connections of combinational logic gates and memories such as flip-flops and latch circuits), which are the subject of the present invention. In the past, a methodology in which test patterns are manually generated (performed as a function test), an automatic test pattern generation (ATPG) methodology in which test patterns are automatically generated by utilizing a scan test technique, and a built-in self test (BIST) methodology in which a test circuit for performing a test is embedded in a LSI have been known for generating test patterns for device under test (DUT). The quality of the test patterns is evaluated by a fault coverage that is a proportion of the number of single stuck-at faults detected by the test patterns to single stuck-at faults (having a number of 2N when there are N nodes or input/output terminals of primitive cells), each one of which is assumed at a node (wire) between basic cells or an input/output terminal of a primitive cell inside the DUT, being fixed to either power supply potential (VDD) or ground potential (GND) of the DUT. The necessary test quality is regarded as being achieved by improving the fault coverage to a required level (95% for instance). In order to cope with the DSM process, it is necessary to increase the required fault coverage closer to 100% (98% for instance). However, with respect to LSIs manufactured by the DSM process, achieving sufficient test quality by only utilizing the stuck-at fault model is difficult.
An essential problem of the concept of the fault coverage of the stuck-at fault model is that the fault coverage only considers the rate of a number of detected faults to the number of supposed faults for the gate net of LSI not having the layout information. Accordingly, it is impossible to obtain correlation of the calculated fault coverage with high precision though it is possible to expect a correlation of the calculated fault coverage (test quality) with fault occurrence of an actual LSI to a certain extent. Furthermore, it is impossible to set appropriate criteria of test quality, so that test patterns tend to be more than necessary. Since it is impossible to add test patterns to highly possible faults based on layout information, sometimes the expected test quality cannot be obtained regardless of the resources for generating and adding test patterns.
Regarding the problem mentioned above, a weighting technique of associating appropriate layout information (layout parameters) with faults, and of estimating the result of a fault simulation as weighted fault coverage has been proposed. As a result, it is possible to improve the precision of correlating process failure rate by adding an appropriate layout weight to a fault following the stuck-at fault model, by executing a fault simulation, and obtaining weighted fault coverage. Moreover, it is possible to effectively reduce resources of adding test patterns by giving clear priority so as to detect undetected faults.
Another essential problem associated with a test utilizing the stuck-at fault model is that the coverage of detected basic faults, such as wire shorts (bridge faults) is unclear though it is possible to check detection of faults of connection nodes or input/output terminals of primitive cells in DUT. Some experimental results in which these basic faults are secondarily detected by improving coverage of stuck-at faults has been reported. However, since improvement of test quality is very difficult in a DSM process, it is difficult to obtain predetermined test quality. With respect to the problem mentioned above, a tool for extracting bridge faults from layout information, and for executing a fault simulation and the ATPG has been recently marketed. Furthermore, in the DSM process, it is necessary to consider an open fault model and a delay fault model.
The test patterns are individually generated in essence only by accumulating a combination of fault models and layout parameters required for maintaining quality of LSIs manufactured by the DSM process. Accordingly, the test pattern size (test pattern length), and the test period (test cost) in a shipping test, greatly increases. However, a technique of effectively reducing test pattern size for the combination of the fault models and the layout parameters has not been proposed.